1. Field
Aspects of embodiments of the present invention generally relate to the field of analog processing and a circuit for performing a convolution operation using pulse domain signals.
2. Related Art
Computer vision techniques are frequently used to analyze images automatically in order to identify objects of interest. These techniques have applications in the control of autonomous robots (e.g., unmanned aerial vehicles and self-driving cars), semi-autonomous robots (e.g., a car that automatically detects hazards and alerts a driver or automatically slows the car in response), target recognition and tracking in military systems (e.g., images from radar, infrared cameras, and visible light cameras), and quality control in manufacturing (e.g., automatic visual analysis of products coming off an assembly line for conformance to standards).
Image processing techniques are often applied to low level data in order to identify features for further analysis by higher level algorithms. For example, image processing can be used to detect high contrast edges within an input image, change the contrast of particular portions of the image, etc.
The convolution function is commonly used in image processing for feature detection. FIG. 1 is a schematic diagram illustrating an example of generating an output image 120 of size 10 pixels by 10 pixels from convolving an input image 100 of size 14 pixels by 14 pixels with a kernel 110 of size 5 pixels by 5 pixels to detect portions (or “patches”) 102 of the input image 100 that are similar to the kernel 110 (one of these patches 102 is shown in dotted lines in FIG. 1). The kernel 110 in this example is a detector of vertical edges that are dark on the left side and light on the right side. Different features can be detected by convolving the input image 100 with various different kernels.
The output image 120 may be generated by splitting the input image 100 into overlapping input patches 102. The values of the pixels in each of the input patches 102 are multiplied by the kernel 110, and the resulting products are added together to generate a single pixel of the output image 120 corresponding to that input patch.
As seen in the output image 120, the image processing image has identified regions in which there is high contrast along a vertical line. For example, the edge between the right side of small black box in the input image 100 and the white area adjacent it (in columns 10 through 12 of the input image 100) corresponds to the dark portion in columns 8 and 9 of the output image 120, and the edge between the gray outer border and the white middle portion of the input image 100 and correspond to the dark portion in column 1 of the output image 120. Furthermore, the left edge of the black square has a white area to its left. This is the “opposite” of the kernel 110 and therefore results in the negative white.
However, implementing the convolution operation can be computationally intensive (e.g., due to the large number of multiplication operations required) and therefore may have high power (energy) requirements when implemented on a general purpose microprocessor. As a result, it may be difficult for a general purpose microprocessor to be able to meet the cost, power, and/or speed requirements of certain applications.
Pulse and spike domain processors have been previously developed to implement generic neural networks, as described, for example, in “Spike domain and pulse domain non-linear processors” U.S. Pat. No. 7,822,698, the entire disclosure of which is incorporated herein by reference. Other work involving pulse and spike domain processors include “Pulse domain encoder and filter circuits” U.S. Pat. No. 7,403,144 and “Spike domain neuron circuit with programmable kinetic dynamic, homeostatic plasticity and axonal delays” U.S. Pat. No. 8,996,431, the entire disclosures of which are incorporated herein by reference.
In addition, circuits that can perform convolutions in the analog domain using Gilbert-type analog multipliers (e.g., a Gilbert cell) to perform convolutions, as described in Cruz, J. M., and L. O. Chua. “A 16×16 cellular neural network universal chip: the first complete single-chip dynamic computer array with distributed memory and with gray-scale input-output.” Analog Integrated Circuits and Signal Processing 15.3 (1998): 227-237. However, the circuits in this paper use a power supply of 5V and the accuracy of the convolutions performed by this design is expected to degrade significantly if scaled to operate at a low voltage.